1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method for forming inter-metal dielectrics (IMD) on a semiconductor substrate.
2. Description of Related Art
With the increased integration in integrated circuits (IC), a conventional wafer can no longer provide sufficient area for interconnects. In order to satisfy performance requirements, design rules of forming more than two metal layers for interconnects are gradually applied in integrated circuits. An inter-metal dielectric (IMD) layer is formed between two metal layers for isolation. Since a metal layer and a dielectric layer are alternately laminated to form metal interconnects, the planarization of the dielectric layer is more important. If the result of the planarization is not ideal, the uneven surface of the dielectric layer causes misalignment while a subsequent photolithography process is performed so that the pattern cannot accurately transfer onto the metal line and the process becomes more difficult.
In general, a spin-on glass (SOG) method is used in metal interconnects fabrication. The method includes coating SOG material on a wafer. Then a curing treatment is performed, in which the unwanted solvent of the SOG material is removed at a high temperature by a thermal treatment to cure the SOG material. Thus, a SOG layer is formed. The SOG material has better step coverage ability and better gap filling ability, therefore, the voids between the metal layers can be easily filled. In SOG application, a sandwich-type structure is provided, in which a dielectric layer made of SOG material is formed between two silicon oxide layers formed by chemical vapor deposition (CVD). Thus, the properties of the SOG layer such as dielectric constant cannot be affected in a subsequent process.
FIGS. 1A through 1B are schematic, cross-sectional views showing a conventional method of forming an inter-metal dielectric layer.
As shown in FIG. 1A, a semiconductor substrate 11 is provided. A metal line 10 is formed over the substrate 11. A silicon oxide layer 12, a SOG layer 14, and a silicon oxide layer 16 are subsequently formed on the metal line 10 to form a sandwich type structure.
Turning to FIG. 1B, a chemical-mechanical polishing (CMP) process is performed to planarize the silicon oxide layer 16. A cap oxide layer 18 is formed on the silicon oxide layer 16 to cover some scratches generated while performing the CMP process. Thus, an inter-metal dielectric layer 19 with a flat surface is formed.
However, while performing the CMP process, no layers, including the SOG layer 14 and the silicon oxide layer 16, are hard enough to serve as a stop layer, therefore the metal line 10 is usually polished and damaged.
One conventional method for solving the above-mentioned problem is to implant ions into the SOG layer after the SOG layer is cured. This implantation makes the cured SOG layer harder, so it can be used as a stop layer. However, in this method, two steps including a curing treatment and an ion implantation are needed so that the process is more complicated, the device throughout is thus decreased and the cost is increased.
Another conventional method is to cure the SOG layer with a high-energy, high-dosage electron beam, so that the metal line is not damaged while performing the CMP process and the metal line is not affected while subsequently forming a via hole. However, although no additional step is added in this method, the dielectric constant of the SOG layer between the two metal layers is increased so as to decrease the isolation effect of the metal line and then, to affect the RC delay time. Moreover, SOG shrinkage adversely affect the planarization of the SOG layer.
Therefore, it is desirable to provide a method which can resolve the above-mentioned problems.